ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies
| Author | : | |
| Rating | : | 4.95 (698 Votes) |
| Asin | : | B073GLNBVL |
| Format Type | : | |
| Number of Pages | : | 395 Pages |
| Publish Date | : | 2015-12-11 |
| Language | : | English |
DESCRIPTION:
He holds 14 U.S. Patents in the field of SoC and 3DIC design verification. Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic Syste
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
Very Good Book on all topics of Functional Verification. The author has done an excellent job and not only providing high level perspective for each topic covered but also real gut level examples/applications to put the high level perspective on concrete ground. A must for Manager types and also a good overview for engineers. Worth the time and money spent.
From the Back Cover This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (Syst